1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
In the case of manufacturing a next-generation complementary metal oxide semiconductor (CMOS) device in which a gate length is a submicron size, there is a high possibility that silicon which has been used in previous generations will not be able to be directly used as a gate electrode of a MIS transistor constituting the device.
One of the reasons of the above is that since sheet resistance of the silicon is as high as several tens Ω/□, a so-called RC delay cannot be ignored any more during a device operation, if the silicon is used for the gate electrode. It is generally considered that in the case of the device in which the gate length is the submicron size, the sheet resistance of the gate electrode which permits the RC delay to be ignored is 5 Ω/□ or less.
Another of the above-mentioned reasons resides in depletion of the gate electrode. A solution limit of impurities (dopants) with respect to silicon is about 1×1020 cm−3. Therefore, when the gate electrode is made of silicon, a depletion layer of a limited length spreads in the gate electrode to cause deterioration in current driving force of the MIS transistor.
Specifically, as this depletion layer has a capacitance to be serially connected to a gate insulating layer between the gate electrode and a channel, a gate capacitance of the MIS transistor is substantially formed into a shape in which the capacitance of the deletion layer is added to the capacitance of the gate insulating layer. For example, when converted into a thickness of silicon oxide of the gate insulating layer, this added capacitance is about 0.3 nm.
It is likely in the future that a thickness of gate insulating layer of the MIS transistor will become 1.5 nm or less when the silicon oxide is used. Thus, the capacitance of the depletion layer will become 20 percent or more of that of the gate insulating layer, which will not be ignored any more.
As one of means to solve the problem, addition of a high concentration of impurities (phosphorus, boron, or the like) to the silicon gate electrode has been tried to reduce its specific resistance. However, in the case of the MIS transistor having the gate length set to the submicron size, the thickness of the gate insulating layer becomes 1.5 nm or less as described above. In this case, a problem occurs in which the impurities in the gate electrode pass through the gate insulating layer to diffuse to or penetrate a silicon substrate.
Such diffusion or penetration of the impurities causes a fluctuation in drive current or threshold voltage of the MIS transistor.
Recently, therefore, use of a high-melting point metal such as molybdenum, tungsten or tantalum, or a nitride thereof for the gate electrode has been tried. This is called a metal gate technology.
According to the metal gate technology, as the gate electrode is made of a metal whose specific resistance is lower than that of the silicon, an RC delay can basically be ignored. As no depletion layer is formed in the metal in principle, no reduction occurs in current driving force of the MIS transistor by the deletion layer formed in the silicon gate. Additionally, as it is not necessary to add any impurities to the metal gate to reduce its specific resistance, no fluctuation occurs in driving force or threshold voltage of the MIS transistor by diffusion or penetration of impurities.
However, the metal gate technology is not perfect. In the case of manufacturing a CMOS device by this technology, the following unique problems occur.
That is, according to the metal gate technology, a metal material having a work function close to that of P+ silicon must be used for a gate electrode in the case of a P-channel MIS transistor. A metal material having a work function close to that of N+-silicon must be used for a gate electrode in the case of an N-channel MIS transistor. This way, it is possible to set threshold values of the P-channel MIS transistor and the N-channel MIS transistor to proper values.
This is called a dual phi (φ) metal gate. In reality, however, it is difficult to discover a metal material having a work function close to that of the P+ silicon or the N+-silicon and high thermal stability. Thus far, no optimal materials that satisfy such conditions have been found for the gate insulating layer or the gate electrode.
Even if a metal material having high thermal stability and proper work function for the gate insulating layer or the gate electrode is discovered, it is useless unless the metal material can be formed by an LSI manufacturing process. In short, in addition to the structure of the MIS transistor by the dual φ metal gate technology, a manufacturing method without any increased number of steps and complexity is demanded.